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Processor of Spatially Predicated Bits

I. Predicate Logic Processor. We are presenting the results concerning the creation of the first synthesized in the hardware predicate logic processor (PLP). It is belongs to the group of application-specific instruction set processors (ASIPs) [1-4]. It is dealing with the predicate expressions represented by spatially–modulated or topologically modulated signals carrying the digital information by their spatial topology and magnitudes of the impulses.

A special type of gates called predicate gates was invented with a very simple design. Then the gates are integrated into larger units composing in this way the processor.

PLP consists of the datapath and control units. It is additionally connected to a RAM (Random Access Memory) module. The datapath is responsible for manipulation of the predicate data. Its core is based on the predicate logic unit (PLU) performing the previously mentioned predicate logic operations. The RAM contains the program code (proposed instructions) and corresponding data. The control unit of the processor is realized as a finite state machine (FSM). By stepping through a sequence of states, this unit controls the operations of the datapath. For each state that this unit is in, it generates an appropriate control signal for datapath to perform one operation.

At the first, a logically full set (AND, OR and NOT) of predicate gates was invented and modeled using VHDL (Very High Speed Integrated Circuit Hardware Description Language). The proposed models are simulated with help of Mentor Graphics ModelSim Software. Then, these gates were synthesized and verified using Altera UP2 (University Program 2) Development Kit, Quartus II software and an oscilloscope.

The architecture of processor was designed and simulated by Quartus II software.  The implemented PLP prototype together with RAM consists of 4916 LE (Logic Elements). It is working with 8-bit data signals and the used clock frequency is equal to 50 MHz. The processor was synthesized using Cyclone II FPGA Altera Starter Development Kit. Theoretical results were compared with the signals generated by the board. The logic level of some selected internal signals is captured by SignalTap II Embedded Logic Analyzer which is a part of the Quartus II software.

II. Conclusions. The first processor based on the predicate logic has been presented. The predicate logic is the basic language of the most database searching machines, Internet servers, artificial intelligence software and holographic imaging systems. The hardware realization allows increasing the database working speed. The presented PLP prototype is considered as the first step towards to the high-speed specialized database processors, Internet servers and other applications based on the predicate logic.

III. References.

1.         G.A. Kouzaev, Topological Computing, WSEAS Trans. Comp., Vol. 5, 2006, pp. 1247-1250.

2.         G.A. Kouzaev and A.N. Kostadinov, Predicate Gates for Spatial Logic, Proc. 11th WSEAS Int. Multiconference CSCC, Agios Nikolaos, Crete Island, Greece, July 23-28, 2007, Vol. 4, Computer Science and Technology, pp. 151-156.

3.         G.A. Kouzaev, Spatial Quasineural Circuits for Electromagnetic Signals, Proc. 12th WSEAS Int. Conf. Circuits, Heraclion, Greece, pp. 218-223, 2008.

4.         A.N. Kostadinov, G.A. Kouzaev, Predicate Logic Processor of spatially Patterned Signals, In: Recent Advances in Systems Engineering and Applied Mathematics, WSEAS Publ., P.94-96, 2008.

G.A. Kouzaev

Department of Electronics and Telecommunications

Norwegian University of Science and Technology

O.S. Bragstads plass 2B, Gloshaugen, Trondheim


A.N. Kostadinov

Department of Electronics, Computer Systems and Automation

John Atanasoff Technical College

25 Tsanko Diustabanov, 4000 Plovdiv